The following invention relates to an active load network for a digital test system for providing proper output loads to a device under test.
Automatic test equipment is frequently employed to run diagnostic tests on integrated circuit devices. The purpose of the testing devices is to ensure that integrated circuits under test provide the proper output voltages given the input stimulus of the tester. It is necessary with such devices to simulate the proper output load, where the output voltage may range from a high logic level voltage (for example, 5 volts) to a low logic level voltage (0 volts). In the past, this function has been accomplished by a diode bridge connected to the output pin of interest of a device under test and current generators connected to opposite arms of the bridge. In order to provide the proper load for the device under test, it is necessary to source current to the device under test when the output is low, and to sink current from the device under test when its output is high. The switching of the diode bridge is controlled by a reference voltage connected to the bridge opposite the input from the device under test. A problem encountered with such devices is the switching speed of the diode bridge when the device under test changes from an inhibited state to either a logic high or a logic low output state. In such instances voltages cannot change quickly across the diode bridge because of the capacitance of the bridge driven by the relatively low current levels provided by the current generators. Thus, the switching between an inhibited output and either high or low logic levels to properly load the device under test is too slow for the current generation of integrated circuit devices.
Another problem with such prior art devices is that they are incapable of pulling the output of the device under test to a predetermined voltage level in the event that the device under test is inhibited.